Messages in this thread | | | From | Anup Patel <> | Date | Thu, 26 Mar 2020 12:35:08 +0530 | Subject | Re: [RFC PATCH 7/7] riscv: Explicit comment about user virtual address space size |
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On Sun, Mar 22, 2020 at 4:37 PM Alexandre Ghiti <alex@ghiti.fr> wrote: > > Define precisely the size of the user accessible virtual space size > for sv32/39/48 mmu types and explain why the whole virtual address > space is split into 2 equal chunks between kernel and user space. > > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > arch/riscv/include/asm/pgtable.h | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 06361db3f486..be117a0b4ea1 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -456,8 +456,15 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) > > /* > - * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. > - * Note that PGDIR_SIZE must evenly divide TASK_SIZE. > + * Task size is: > + * - 0x9fc00000 (~2.5GB) for RV32. > + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu > + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu > + * > + * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V > + * Instruction Set Manual Volume II: Privileged Architecture" states that > + * "load and store effective addresses, which are 64bits, must have bits > + * 63–48 all equal to bit 47, or else a page-fault exception will occur." > */ > #ifdef CONFIG_64BIT > #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) > -- > 2.20.1 >
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards, Anup
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