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    Subject[PATCH v6 2/3] clk: qcom: gcc: Add support for modem clocks in GCC
    Date
    Add the required modem clocks in global clock controller which are
    required to bring the modem out of reset.

    Signed-off-by: Taniya Das <tdas@codeaurora.org>
    ---
    drivers/clk/qcom/gcc-sc7180.c | 72 ++++++++++++++++++++++++++++++++++++++++++-
    1 file changed, 71 insertions(+), 1 deletion(-)

    diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
    index 7f59fb8..6a51b5b 100644
    --- a/drivers/clk/qcom/gcc-sc7180.c
    +++ b/drivers/clk/qcom/gcc-sc7180.c
    @@ -1,6 +1,6 @@
    // SPDX-License-Identifier: GPL-2.0-only
    /*
    - * Copyright (c) 2019, The Linux Foundation. All rights reserved.
    + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
    */

    #include <linux/clk-provider.h>
    @@ -2165,6 +2165,71 @@ static struct clk_branch gcc_video_xo_clk = {
    },
    };

    +static struct clk_branch gcc_mss_cfg_ahb_clk = {
    + .halt_reg = 0x8a000,
    + .halt_check = BRANCH_HALT,
    + .clkr = {
    + .enable_reg = 0x8a000,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_mss_cfg_ahb_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_mss_mfab_axis_clk = {
    + .halt_reg = 0x8a004,
    + .halt_check = BRANCH_HALT_VOTED,
    + .clkr = {
    + .enable_reg = 0x8a004,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_mss_mfab_axis_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_mss_nav_axi_clk = {
    + .halt_reg = 0x8a00c,
    + .halt_check = BRANCH_HALT_VOTED,
    + .clkr = {
    + .enable_reg = 0x8a00c,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_mss_nav_axi_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_mss_snoc_axi_clk = {
    + .halt_reg = 0x8a150,
    + .halt_check = BRANCH_HALT,
    + .clkr = {
    + .enable_reg = 0x8a150,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_mss_snoc_axi_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
    + .halt_reg = 0x8a154,
    + .halt_check = BRANCH_HALT,
    + .clkr = {
    + .enable_reg = 0x8a154,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_mss_q6_memnoc_axi_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct gdsc ufs_phy_gdsc = {
    .gdscr = 0x77004,
    .pd = {
    @@ -2336,6 +2401,11 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
    [GPLL7] = &gpll7.clkr,
    [GPLL4] = &gpll4.clkr,
    [GPLL1] = &gpll1.clkr,
    + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
    + [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
    + [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
    + [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
    + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
    };

    static const struct qcom_reset_map gcc_sc7180_resets[] = {
    --
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    of the Code Aurora Forum, hosted by the Linux Foundation.
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