Messages in this thread | | | Date | Wed, 9 Dec 2020 14:09:21 +0530 | From | Srikar Dronamraju <> | Subject | Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache |
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* Gautham R Shenoy <ego@linux.vnet.ibm.com> [2020-12-08 23:26:47]:
> > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not > > be released. Is this as expected? > > cacheinfo populates the cache->shared_cpu_map on the basis of which > CPUs share the common device-tree node for a particular cache. There > is one l1-cache object in the device-tree for a CPU node corresponding > to a big-core. That the L1 is further split between the threads of the > core is shown using ibm,thread-groups. >
Yes.
> The ideal thing would be to add a "group_leader" field to "struct > cache" so that we can create separate cache objects , one per thread > group. I will take a stab at this in the v2. >
I am not saying this needs to be done immediately. We could add a TODO and get it done later. Your patch is not making it worse. Its just that there is still something more left to be done.
-- Thanks and Regards Srikar Dronamraju
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