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    SubjectRe: [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn
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    On 11/2/20 9:46 PM, Mathieu Poirier wrote:
    > Hi Suzuki,
    >
    > On Wed, Oct 28, 2020 at 10:09:25PM +0000, Suzuki K Poulose wrote:
    >> TRCSSPCICR<n> is present only if all of the following are true:
    >> TRCIDR4.NUMSSCC > n.
    >> TRCIDR4.NUMPC > 0b0000 .
    >> TRCSSCSR<n>.PC == 0b1
    >>
    >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    >> ---
    >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 ++++++++-----
    >> 1 file changed, 8 insertions(+), 5 deletions(-)
    >>
    >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
    >> index d78a37b6592c..0310eac9dc16 100644
    >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
    >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
    >> @@ -175,8 +175,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
    >> drvdata->base + TRCSSCCRn(i));
    >> writel_relaxed(config->ss_status[i],
    >> drvdata->base + TRCSSCSRn(i));
    >> - writel_relaxed(config->ss_pe_cmp[i],
    >> - drvdata->base + TRCSSPCICRn(i));
    >> + if (drvdata->nr_pe)
    >
    > Aren't you missing to check the value of the PC bit in TRCSSCSRn?
    >
    > /*
    > * TRCSSCSRn:PC, bit[3]: Indidate support for single-shot PE
    > * comparator input.
    > */
    > if (drvdata->nr_pe && (config->ss_status[i] & BIT(3)))
    >
    >

    You're right. Thank for catching this. I will update the series and drop
    the patches 1-5.


    > I have picked up patches 1 to 5 and added a "Cc:stable" to paches 2, 4 and 5.
    > More comments to come tomorrow.

    Thanks !
    Suzuki

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