Messages in this thread | | | From | "Lendacky, Thomas" <> | Subject | Re: setup_boot_APIC_clock() NULL dereference during early boot on reduced hardware platforms | Date | Thu, 8 Aug 2019 21:36:05 +0000 |
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Hi Thomas,
On 8/8/19 4:08 PM, Thomas Gleixner wrote: > Tom, > > On Thu, 8 Aug 2019, Lendacky, Thomas wrote: >> On 8/8/19 3:36 PM, Thomas Gleixner wrote: >>> On Thu, 1 Aug 2019, Lendacky, Thomas wrote: >>>> On 8/1/19 5:13 AM, Thomas Gleixner wrote: >>>>> 2.1.9 Timers >>>>> >>>>> Each core includes the following timers. These timers do not vary in >>>>> frequency regardless of the current P-state or C-state. >>>>> >>>>> * Core::X86::Msr::TSC; the TSC increments at the rate specified by the >>>>> P0 Pstate. See Core::X86::Msr::PStateDef. >>>>> >>>>> * The APIC timer (Core::X86::Apic::TimerInitialCount and >>>>> Core::X86::Apic::TimerCurrentCount), which increments at the rate of >>>>> 2xCLKIN; the APIC timer may increment in units of between 1 and 8. >>>>> >>>>> The Ryzens use a 100MHz input clock for the APIC normally, but I'm not sure >>>>> whether this is subject to overclocking. If so then it should be possible >>>>> to figure that out somehow. Tom? >>>> >>>> Let me check with the hardware folks and I'll get back to you. >>> >>> any update on this? The problem seems to come in from several sides now. >> >> Yes, sort of. There are two ways to overclock and it all depends on which >> one was used. If the overclocking is done by changing the multipliers, >> then that 100MHz clock will still be 100MHz. But if the overclocking is >> done by increasing the input clock, then that 100MHz clock will also >> increase. >> >> I was trying to get a bit more clarification on this before replying, but >> it can be detected in software. The base clock is 100MHz, so read the P0 >> multiplier and the TSC should be counting at P0 * 100MHz. If you calibrate >> the speed of the TSC with the HPET you can see what speed the TSC is >> counting at. If you divide the TSC delta from the HPET calibration by the >> P0 multiplier you will either get 100MHz if there is no overclocking or if >> the multiplier method of overclocking was used, otherwise you'll get a >> higher value if the input clock method was used. Either way, that should >> give you the APIC clock speed based on a starting assumption of 100MHz. > > The problem is that we have no HPET on those machines ....
Sorry about that... I interpreted the email[1] that said the HPET ACPI table was present, incorrectly. I get it now, for hardware-reduced ACPI you can't depend on that table to be present.
Thanks, Tom
[1] https://lore.kernel.org/lkml/CAD8Lp452GdoL-Bt7rSP=u3RKEZ2H3qm3LvKfe=cCsjP0biG_sQ@mail.gmail.com/
> > I think I can get away without having HPET and PIT and do some smart stuff > with the pm timer for that stuff. I'll look at it tomorrow with brain > actually awake. > > Thanks, > > tglx > > > > >
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