Messages in this thread | | | Subject | Re: [PATCH v2 2/2] clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU | From | Stephen Boyd <> | Date | Thu, 08 Aug 2019 13:54:30 -0700 |
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Quoting Sylwester Nawrocki (2019-08-08 07:49:29) > This patch fixes broken sound on Exynos5422/5800 platforms after > system/suspend resume cycle in cases where the audio root clock > is derived from MAU_EPLL_CLK. > > In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux > during system suspend/resume cycle for Exynos5800 we group the MAU > block input clocks in "MAU" sub-CMU and add the clock mux control > bit to .suspend_regs. This ensures that user configuration of the mux > is not lost after the PMU block changes the mux setting to OSC_DIV > when switching off the MAU power domain. > > Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not > sufficient as at the time of the syscore_ops suspend call MAU power > domain is already turned off and we already save and subsequently > restore an incorrect register's value. > > Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") > Reported-by: Jaafar Ali <jaafarkhalaf@gmail.com> > Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> > Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > ---
Applied to clk-fixes
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