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    SubjectRe: [PATCH v2 3/3] dwc: PCI: intel: Intel PCIe RC controller driver
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    Hi Martin,

    On 8/27/2019 11:09 AM, Chuan Hua, Lei wrote:
    [...]
    >
    >
    >> now I am wondering:
    >> - if we don't have to disable the interrupt line (once it is enabled),
    >> why can't we enable all of these interrupts at initialization time
    >> (instead of doing it on-demand)?
    > Good point! we even can remote map_irq patch, directly call
    >
    > of_irq_parse_and_map_pci as other drivers do.

    Irrespective of disabling, imo interrupts(A/B/C/D) should be enabled
    when they are requested; which happens during map_irq() call.

    >> - if the interrupts do have to be disabled again (that is what I
    >> assumed so far) then where is this supposed to happen? (my solution
    >> for this was to implement a simple interrupt controller within the
    >> PCIe driver which only supports enable/disable. disclaimer: I didn't
    >> ask the PCI or interrupt maintainers for feedback on this yet)
    >>
    >> [...]
    >
    > We can implement one interrupt controller, but personally, it has too
    >
    > much overhead. If we follow this way, almost all modules of all old
    >
    > lantiq SoCs can implement one interrupt controller. Maybe you can check
    >
    > with PCI maintainer for their comments.
    >
    [...]
    >>> This is needed. In the old driver, we fixed this by fixup. The original
    >>> comment as follows,
    >>>
    >>> /*
    >>>    * The root complex has a hardwired class of
    >>> PCI_CLASS_NETWORK_OTHER or
    >>>    * PCI_CLASS_BRIDGE_HOST, when it is operating as a root complex this
    >>>    * needs to be switched to * PCI_CLASS_BRIDGE_PCI
    >>>    */
    >> that would be a good comment to add if you really need it
    >> can you please look at dw_pcie_setup_rc (from
    >> pcie-designware-host.c), it does:
    >>    /* Enable write permission for the DBI read-only register */
    >>    dw_pcie_dbi_ro_wr_en(pci);
    >>    /* Program correct class for RC */
    >>    dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
    >>    /* Better disable write permission right after the update */
    >>    dw_pcie_dbi_ro_wr_dis(pci);
    >>
    >> so my understanding is that there is a functional requirement to set
    >> the class to PCI_CLASS_BRIDGE_PCI
    >> however, that requirement is already covered by pcie-designware-host.c
    > I will task Dilip to check if we can use dwc one.
    dw_pcie_setup_rc () cannot be called here because, it is not doing
    PCI_CLASS_BRIDGE_PCI set alone, it is configuring many other things.

    [...]


    Regards,

    Dilip

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