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    Subject[PATCH 5.2 125/144] drm/i915: Fix wrong escape clock divisor init for GLK
    Date
    From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

    commit 73a0ff0b30af79bf0303d557eb82f1d1945bb6ee upstream.

    According to Bspec clock divisor registers in GeminiLake
    should be initialized by shifting 1(<<) to amount of correspondent
    divisor. While i915 was writing all this time that value as is.

    Surprisingly that it by accident worked, until we met some issues
    with Microtech Etab.

    v2: Added Fixes tag and cc
    v3: Added stable to cc as well.

    Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
    Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826
    Fixes: bcc657004841 ("drm/i915/glk: Program txesc clock divider for GLK")
    Cc: Deepak M <m.deepak@intel.com>
    Cc: Madhav Chauhan <madhav.chauhan@intel.com>
    Cc: Jani Nikula <jani.nikula@intel.com>
    Cc: Jani Nikula <jani.nikula@linux.intel.com>
    Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Cc: intel-gfx@lists.freedesktop.org
    Cc: stable@vger.kernel.org
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190712081938.14185-1-stanislav.lisovskiy@intel.com
    (cherry picked from commit ce52ad5dd52cfaf3398058384e0ff94134bbd89c)
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/i915/vlv_dsi_pll.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
    +++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
    @@ -394,8 +394,8 @@ static void glk_dsi_program_esc_clock(st
    else
    txesc2_div = 10;

    - I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
    - I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
    + I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
    + I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
    }

    /* Program BXT Mipi clocks and dividers */

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