lkml.org 
[lkml]   [2019]   [Aug]   [13]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v8 3/4] mtd: spi-nor: add support to unlock the flash device
    Date
    Nor device (is25wp256 mounted on HiFive unleashed Rev A00 board) from ISSI
    have memory blocks guarded by block protection bits BP[0,1,2,3].
    Add an identifier within the flash info structure to indicate that a
    particular flash device has the fourth block protect bit (SPI_NOR_HAS_BP3).

    Increase size of flash_info flags from u16 to u32 to avoid flag overflow
    due SPI_NOR_HAS_BP3.
    Clear block protection bits unlocks the flash memory regions.

    Based on code developed by Wesley Terpstra <wesley@sifive.com>
    and/or Palmer Dabbelt <palmer@sifive.com>.
    https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b

    spell correction: "Configuration" in spansion_quad_enable function
    description.

    Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
    ---
    drivers/mtd/spi-nor/spi-nor.c | 72 ++++++++++++++++++++++++++++++++++++++++---
    include/linux/mtd/spi-nor.h | 2 ++
    2 files changed, 70 insertions(+), 4 deletions(-)

    diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
    index cb40b1b..24c1c11 100644
    --- a/drivers/mtd/spi-nor/spi-nor.c
    +++ b/drivers/mtd/spi-nor/spi-nor.c
    @@ -250,7 +250,7 @@ struct flash_info {
    u16 page_size;
    u16 addr_width;

    - u16 flags;
    + u32 flags;
    #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
    #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
    #define SST_WRITE BIT(2) /* use SST byte programming */
    @@ -279,6 +279,13 @@ struct flash_info {
    #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
    #define USE_CLSR BIT(14) /* use CLSR command */
    #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
    +#define SPI_NOR_HAS_BP3 BIT(16) /*
    + * Flash SR has block protect bits
    + * for lock/unlock purpose, few support
    + * BP0-BP2 while few support BP0-BP3.
    + * This flag identifies devices that
    + * support BP3 bit.
    + */

    /* Part specific fixup hooks. */
    const struct spi_nor_fixups *fixups;
    @@ -1461,7 +1468,55 @@ static int macronix_quad_enable(struct spi_nor *nor)
    }

    /**
    - * spansion_quad_enable() - set QE bit in Configuraiton Register.
    + * issi_unlock() - clear BP[0123] write-protection.
    + * @nor: pointer to a 'struct spi_nor'.
    + * @ofs: offset from which to unlock memory.
    + * @len: number of bytes to unlock.
    + *
    + * Bits [2345] of the Status Register are BP[0123].
    + * ISSI chips use a different block protection scheme than other chips.
    + * Just disable the write-protect unilaterally.
    + *
    + * Return: 0 on success, -errno otherwise.
    + */
    +static int issi_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
    +{
    + int ret, val;
    + u8 mask;
    +
    + if (nor->flags & SNOR_F_HAS_BP3)
    + mask = SR_BP3 | SR_BP2 | SR_BP1 | SR_BP0;
    + else
    + mask = SR_BP2 | SR_BP1 | SR_BP0;
    +
    + val = read_sr(nor);
    + if (val < 0)
    + return val;
    + if (!(val & mask))
    + return 0;
    +
    + write_enable(nor);
    +
    + write_sr(nor, val & ~mask);
    +
    + ret = spi_nor_wait_till_ready(nor);
    + if (ret)
    + return ret;
    +
    + ret = read_sr(nor);
    + if (ret > 0 && !(ret & mask)) {
    + dev_info(nor->dev, "ISSI block protect bits cleared SR: 0x%x\n",
    + ret);
    + ret = 0;
    + } else {
    + dev_err(nor->dev, "ISSI block protect bits not cleared\n");
    + ret = -EINVAL;
    + }
    + return ret;
    +}
    +
    +/**
    + * spansion_quad_enable() - set QE bit in Configuration Register.
    * @nor: pointer to a 'struct spi_nor'
    *
    * Set the Quad Enable (QE) bit in the Configuration Register.
    @@ -1948,8 +2003,10 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
    { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 1024,
    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
    - SPI_NOR_4B_OPCODES)
    - .fixups = &is25lp256_fixups },
    + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
    + SPI_NOR_HAS_BP3)
    + .fixups = &is25lp256_fixups
    + },
    /* Macronix */
    { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
    { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
    @@ -4207,6 +4264,13 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
    nor->flash_is_locked = stm_is_locked;
    }

    + /* NOR protection support for ISSI chips */
    + if (JEDEC_MFR(info) == SNOR_MFR_ISSI &&
    + info->flags & SPI_NOR_HAS_LOCK &&
    + info->flags & SPI_NOR_HAS_BP3) {
    + nor->flash_unlock = issi_unlock;
    + }
    +
    if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
    mtd->_lock = spi_nor_lock;
    mtd->_unlock = spi_nor_unlock;
    diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
    index 5d6583e..4f92dbb 100644
    --- a/include/linux/mtd/spi-nor.h
    +++ b/include/linux/mtd/spi-nor.h
    @@ -127,6 +127,7 @@
    #define SR_BP0 BIT(2) /* Block protect 0 */
    #define SR_BP1 BIT(3) /* Block protect 1 */
    #define SR_BP2 BIT(4) /* Block protect 2 */
    +#define SR_BP3 BIT(5) /* Block protect 3 */
    #define SR_TB BIT(5) /* Top/Bottom protect */
    #define SR_SRWD BIT(7) /* SR write protect */
    /* Spansion/Cypress specific status bits */
    @@ -244,6 +245,7 @@ enum spi_nor_option_flags {
    SNOR_F_BROKEN_RESET = BIT(6),
    SNOR_F_4B_OPCODES = BIT(7),
    SNOR_F_HAS_4BAIT = BIT(8),
    + SNOR_F_HAS_BP3 = BIT(9),
    };

    /**
    --
    1.9.1
    \
     
     \ /
      Last update: 2019-08-13 14:40    [W:4.158 / U:0.016 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site