Messages in this thread | | | Date | Wed, 14 Aug 2019 09:07:08 +0800 | From | Alan Kao <> | Subject | Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting |
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Please ignore the previous mail, I must have missed this part of the patch, > > > + csrr t0, CSR_MISA > > + andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) > > + bnez t0, .Lreset_regs_done > > +
In S-mode we were not able to obtain the ISA information in misa, but now the nommu port is in M-mode so this is rather straightforward.
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