Messages in this thread | | | Date | Wed, 26 Jun 2019 09:55:31 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 1/2 RESEND2] perf/x86/amd/uncore: Do not set ThreadMask and SliceMask for non-L3 PMCs |
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On Tue, Jun 25, 2019 at 02:56:23PM +0000, Phillips, Kim wrote: > From: Kim Phillips <kim.phillips@amd.com> > > Commit d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask > for L3 Cache perf events") enables L3 PMC events for all threads and > slices by writing 1s in ChL3PmcCfg (L3 PMC PERF_CTL) register fields. > > Those bitfields overlap with high order event select bits in the Data > Fabric PMC control register, however. > > So when a user requests raw Data Fabric events (-e amd_df/event=0xYYY/), > the two highest order bits get inadvertently set, changing the counter > select to events that don't exist, and for which no counts are read. > > This patch changes the logic to write the L3 masks only when dealing > with L3 PMC counters. > > AMD Family 16h and below Northbridge (NB) counters were not affected. > > Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Still base64 encoded garbage; the actual email reads like below.
Please use a sane MUa and send it plain text.
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Content-Transfer-Encoding: base64
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