Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH] drivers: clk: Update clock driver to handle clock attribute | Date | Thu, 11 Apr 2019 11:32:50 -0700 |
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Quoting Jolly Shah (2019-03-04 15:19:10) > From: Rajan Vaja <rajan.vaja@xilinx.com> > > Versal EEMI APIs uses clock device ID which is combination of class, > subclass, type and clock index (e.g. 0x8104006 in which 0-13 bits are > for index(6 in given example), 14-19 bits are for clock type (i.e pll, > out or ref, 1 in given example), 20-25 bits are for subclass which is > nothing but clock type only), 26-32 bits are for device class, which > is clock(0x2) for all clocks) while zynqmp firmware uses clock ID > which is index only (e.g 0, 1, to n, where n is max_clock id). > > To use zynqmp clock driver for versal platform also, extend use > of QueryAttribute API to fetch device class, subclass and clock type > to create clock device ID. In case of zynqmp this attributes would be > 0 only, so there won't be any effect on clock id as it would use > clock index only. > > Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > Signed-off-by: Jolly Shah <jollys@xilinx.com> > ---
Applied to clk-next
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