Messages in this thread | | | Date | Sun, 31 Mar 2019 20:47:30 +0200 | From | Uwe Kleine-König <> | Subject | Re: [PATCH 0/1] pwm: meson: fix scheduling while atomic issue |
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On Sat, Mar 30, 2019 at 08:29:35PM +0100, Martin Blumenstingl wrote: > Hello Uwe, > > On Mon, Mar 25, 2019 at 9:07 PM Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: > [...] > > > > - Does stopping the PWM (i.e. clearing MISC_{A,B}_EN in the MISC_AB > > > > register) freeze the output, or is the currently running period > > > > completed first? (The latter is the right behaviour.) > > > I don't know, I would have to measure this with a logic analyzer. > > > > In practise you can do this with a multimeter, too. Just do something > > like: > > > > pwm_apply_state({ .enabled = true, .period = 5s, .duty_cycle = 5s, .polarity = PWM_POLARITY_NORMAL }); > > pwm_apply_state({ .enabled = false, .period = 5s, .duty_cycle = 5s, .polarity = PWM_POLARITY_NORMAL }); > > > > (assuming the PWM supports periods that long). The expectation is that > > the last command takes nearly 5 s to complete and while it waits the > > output is high and on return it's low. If that isn't the case, there is > > a bug somewhere. > the longest supported period (using the 24MHz crystal as input, which > is the slowest input clock and thus gives the longest possible > duration) is 349514407ns (that's approx. 0.35 seconds). my multimeter > isn't fast enough to measure this so I'm using my logic analyzer with > puleseview instead: [0] > > I added the following code to meson_pwm_request: > struct pwm_state enable = { > .enabled = true, > .period = 349514407U, > .duty_cycle = 349514407U, > .polarity = PWM_POLARITY_NORMAL }; > struct pwm_state disable = { > .enabled = false, > .period = 349514407U, > .duty_cycle = 349514407U, > .polarity = PWM_POLARITY_NORMAL }; > pwm_apply_state(pwm, &enable); > pwm_apply_state(pwm, &disable); > > this returns immediately. my logic analyzer doesn't see signal change > (I'm sampling at 1MHz). > > can you please confirm that my test code and measurement procedure is correct? > if it is then my observation is that disabling the PWM does so > immediately, without waiting for the current period to complete
Ack, with the above two pwm_apply_state the output must be high when the first pwm_apply_state returns. Then it must stay high for n * 349514407 ns (for an natural n >= 1) and then go low.
Best regards Uwe
-- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |
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