Messages in this thread | | | Subject | Re: [PATCH RFC 3/6] clk: meson: g12a: mark fclk_div3 as critical | From | Jerome Brunet <> | Date | Wed, 27 Mar 2019 11:51:42 +0100 |
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On Wed, 2019-03-27 at 11:33 +0100, Neil Armstrong wrote: > On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for > the system to operate correctly. > > Disabling it cause the entire system to freeze, including peripherals. > > This patch patch marks this clock as critical, fixing boot on G12b platforms. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/clk/meson/g12a.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index 03b4c78f558f..d62ebcd2162d 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -1062,6 +1062,16 @@ static struct clk_fixed_factor g12a_fclk_div3_div = { > .ops = &clk_fixed_factor_ops, > .parent_names = (const char *[]){ "fixed_pll" }, > .num_parents = 1, > + /* > + * This clock is used by the resident firmware and is required > + * by the platform to operate correctly. > + * Until the following condition are met, we need this clock to > + * be marked as critical: > + * a) Mark the clock used by a firmware resource, if possible > + * b) CCF has a clock hand-off mechanism to make the sure the > + * clock stays on until the proper driver comes along > + */ > + .flags = CLK_IS_CRITICAL,
The gate should be critical then, not the fixed_divider clock. the fdiv3 gate is a child of this clock, so fdiv3 should still be able to gate with this
> }, > }; > >
Could you CC me of the whole series next time, I prefer getting the all context.
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