Messages in this thread | ![/](/images/icornerl.gif) | | Subject | Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value | From | Peter Geis <> | Date | Thu, 9 Aug 2018 08:23:16 -0400 |
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On 08/09/2018 08:02 AM, Aapo Vienamo wrote: > On Thu, 9 Aug 2018 13:49:22 +0200 > Thierry Reding <thierry.reding@gmail.com> wrote: > >> On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote: >>> Add the HS400 DQS trim value for Tegra186 SDMMC4. >>> >>> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> >>> --- >>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi >>> index 6e9ef26..9e07bc6 100644 >>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi >>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi >>> @@ -313,6 +313,7 @@ >>> nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; >>> nvidia,default-tap = <0x5>; >>> nvidia,default-trim = <0x9>; >>> + nvidia,dqs-trim = <63>; >>> status = "disabled"; >>> }; >>> >> >> Isn't this technically dependent on the board layout and as such would >> belong in the board DTS file? Or does this value work on all existing >> Tegra186 platforms? > > This value is specified as part of the controller initialization > sequence in the TRM. I've understood that this (and other tap and trim) > value(s) are used for compensating the propagation delay differences > that are caused by the internal SoC layout. > > -Aapo > --
The Tegra2 and Tegra3 TRMs also specify recommended DQS values, and I am working on at least one device that differs in the platform data from the default value. I see that you mentioned this is for the newer devices that support HS200/HS400 modes, but does it enable setting DQS on older devices?
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