Messages in this thread | | | Date | Sat, 7 Jul 2018 19:51:09 +0800 | From | Guo Ren <> | Subject | Re: [PATCH V2 06/19] csky: Cache and TLB routines |
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On Thu, Jul 05, 2018 at 07:40:25PM +0200, Peter Zijlstra wrote: > > +#ifdef CONFIG_SMP > > +#define mb() asm volatile ("sync.is":::"memory") > > +#else > > +#define mb() asm volatile ("sync":::"memory") > > +#endif > > This is very suspect, please elaborate. > > What I would've expected is: > > #define mb() asm volatile ("sync" ::: "memory") > > #ifdef CONFIG_SMP > #define __smp_mb() asm volatile ("sync.is" ::: "memory") > #endif > > Is that in fact what you meant? > > Do you have a reference to your architecture manual and memory model > description somewhere? I'll fixup it in next version patch.
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