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    SubjectRe: [PATCH V2 06/19] csky: Cache and TLB routines
    On Mon, Jul 02, 2018 at 01:30:09AM +0800, Guo Ren wrote:
    > diff --git a/arch/csky/include/asm/barrier.h b/arch/csky/include/asm/barrier.h
    > new file mode 100644
    > index 0000000..7254527
    > --- /dev/null
    > +++ b/arch/csky/include/asm/barrier.h
    > @@ -0,0 +1,19 @@
    > +// SPDX-License-Identifier: GPL-2.0
    > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
    > +#ifndef __ASM_CSKY_BARRIER_H
    > +#define __ASM_CSKY_BARRIER_H
    > +
    > +#ifndef __ASSEMBLY__
    > +
    > +#define nop() asm volatile ("nop")
    > +
    > +#ifdef CONFIG_SMP
    > +#define mb() asm volatile ("sync.is":::"memory")
    > +#else
    > +#define mb() asm volatile ("sync":::"memory")
    > +#endif

    This is very suspect, please elaborate.

    What I would've expected is:

    #define mb() asm volatile ("sync" ::: "memory")

    #ifdef CONFIG_SMP
    #define __smp_mb() asm volatile ("sync.is" ::: "memory")
    #endif

    Is that in fact what you meant?

    Do you have a reference to your architecture manual and memory model
    description somewhere?


    > +
    > +#include <asm-generic/barrier.h>
    > +
    > +#endif /* __ASSEMBLY__ */
    > +#endif /* __ASM_CSKY_BARRIER_H */

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