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    SubjectRe: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
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    On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote:
    > > We could even add ranges instead of table when we know the PLL supports a well-known continuous dividers range.
    >
    > I had a look at the sys_pll settings on Meson8b, here's what
    > Meson8/Meson8b/Meson8m2 support for sys_pll:
    > - 50..74
    > - 76
    > - 78
    > - 80
    > - 82
    > - 84
    > - 86
    > - 88
    > - 90
    > - 92
    > - 94
    > - 96
    > - 98

    Are those values with the same predivider (n) value ?
    I suspect the ability of the DCO to lock might depends on its input rate and an
    m range

    So if n change, it might possible that the m range will be different.

    ... at least, that's my guess :)

    >
    > (I'm providing this info because it may help finding a decision
    > whether ranges are good or not. I have no preference)

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