Messages in this thread | | | Date | Wed, 11 Jul 2018 12:55:46 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH V2] MIPS: implement smp_cond_load_acquire() for Loongson-3 |
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On Wed, Jul 11, 2018 at 10:04:52AM +0000, David Laight wrote: > I also suspect that 'write starvation' is also common - after all the > purpose of the store buffer is to do reads in preference to writes in > order to reduce the cpu stalls waiting for the memory bus (probably > the cpu to cache interface). > > I think your example is just: > *(volatile int *)xxx = 1; > while (!*(volatile int *)yyy) continue; > running on two cpu with xxx and yyy swapped?
Yep. And Linux has been relying on that working for (afaict) basically forever.
> You need a stronger bus cycle in there somewhere.
Since all spin-wait loops _should_ have cpu_relax() that is the natural place to put it.
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