Messages in this thread | | | From | Dan Williams <> | Date | Tue, 5 Jun 2018 19:00:14 -0700 | Subject | Re: [PATCH v2 3/3] libnvdimm: don't flush power-fail protected CPU caches |
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On Tue, Jun 5, 2018 at 4:58 PM, Ross Zwisler <ross.zwisler@linux.intel.com> wrote: > This commit: > > 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()") > > intended to make sure that deep flush was always available even on > platforms which support a power-fail protected CPU cache. An unintended > side effect of this change was that we also lost the ability to skip > flushing CPU caches on those power-fail protected CPU cache. > > Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> > Fixes: 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()") > --- > drivers/dax/super.c | 14 +++++++++++++- > drivers/nvdimm/pmem.c | 2 ++ > include/linux/dax.h | 4 ++++ > 3 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/dax/super.c b/drivers/dax/super.c > index c2c46f96b18c..80253c531a9b 100644 > --- a/drivers/dax/super.c > +++ b/drivers/dax/super.c > @@ -152,6 +152,8 @@ enum dax_device_flags { > DAXDEV_ALIVE, > /* gate whether dax_flush() calls the low level flush routine */ > DAXDEV_WRITE_CACHE, > + /* only flush the CPU caches if they are not power fail protected */ > + DAXDEV_FLUSH_ON_SYNC,
I'm not grokking why we need DAXDEV_FLUSH_ON_SYNC. The power fail protected status of the cache only determines the default for DAXDEV_WRITE_CACHE.
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