Messages in this thread | | | Subject | Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too | From | Marek Vasut <> | Date | Wed, 20 Jun 2018 06:52:09 +0200 |
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On 06/19/2018 02:07 PM, Richard Weinberger wrote: > The denali NAND flash controller needs at least two clocks to operate, > nand_clk and nand_x_clk. > Since 1bb88666775e ("mtd: nand: denali: handle timing parameters by > setup_data_interface()") nand_x_clk is used to derive timing settings. > > Signed-off-by: Richard Weinberger <richard@nod.at> > --- > Strictly speaking denali needs a ecc_clk too, but AFAIK such a clock > is not present on this SoC. > But my SoCFPGA knowledge is very limited. > > Thanks, > //richard
It looks sane, but I cannot test it right now, since I'm on vacation. I hope Dinh/Chin can jump in.
> --- > arch/arm/boot/dts/socfpga.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index 486d4e7433ed..562f7b375bbd 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -754,7 +754,8 @@ > reg-names = "nand_data", "denali_reg"; > interrupts = <0x0 0x90 0x4>; > dma-mask = <0xffffffff>; > - clocks = <&nand_clk>; > + clocks = <&nand_clk>, <&nand_x_clk>; > + clock-names = "nand", "nand_x"; > status = "disabled"; > }; > >
-- Best regards, Marek Vasut
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