Messages in this thread | | | Subject | Re: [PATCH v1 3/4] clk: tegra20: Turn EMC clock gate into divider | From | Dmitry Osipenko <> | Date | Sat, 2 Jun 2018 14:00:18 +0300 |
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On 02.06.2018 09:37, Stephen Boyd wrote: > Quoting Dmitry Osipenko (2018-05-30 08:06:45) >> Kernel should never gate the EMC clock as it causes immediate lockup, so >> removing clk-gate functionality doesn't affect anything. Turning EMC clk >> gate into divider allows to implement glitch-less EMC scaling, avoiding >> reparenting to a backup clock. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > > Looks ok to me, but I'm waiting for someone from Tegra side to ack it or > review it. >
I've already prepared v2 with some minor cleanups and additional clk patch. For now waiting for Peter's review comments to v1.
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