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    Subject[PATCH 4.16 266/279] clk: imx6ull: use OSC clock during AXI rate change
    Date
    4.16-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Stefan Agner <stefan@agner.ch>

    [ Upstream commit 2e5be528ab0182ad4b42b9feea3b80f85f37179b ]

    On i.MX6 ULL using PLL3 seems to cause a freeze when setting
    the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
    since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
    for busy divider and busy mux"), probably because the clock is
    now forced to be on.

    Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
    Signed-off-by: Stefan Agner <stefan@agner.ch>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/clk/imx/clk-imx6ul.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/clk/imx/clk-imx6ul.c
    +++ b/drivers/clk/imx/clk-imx6ul.c
    @@ -461,7 +461,7 @@ static void __init imx6ul_clocks_init(st
    clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);

    /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
    - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
    + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
    clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
    clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
    clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);

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