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    Subject[PATCH 4.14 187/496] drm/amd/amdgpu: Correct VRAM width for APUs with GMC9
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Tom St Denis <tom.stdenis@amd.com>

    [ Upstream commit 585b7f161c85bd5ca675b97580faf21c506541e3 ]

    DDR4 has a 64-bit width not 128-bits. It was reporting
    twice the width. Tested with my Ryzen 2400G.

    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 ++++-
    1 file changed, 4 insertions(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    @@ -456,7 +456,10 @@ static int gmc_v9_0_mc_init(struct amdgp
    adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
    if (!adev->mc.vram_width) {
    /* hbm memory channel size */
    - chansize = 128;
    + if (adev->flags & AMD_IS_APU)
    + chansize = 64;
    + else
    + chansize = 128;

    tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
    tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;

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