lkml.org 
[lkml]   [2018]   [May]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.16 074/161] usb: dwc2: host: Fix transaction errors in host mode
    Date
    4.16-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Minas Harutyunyan <hminas@synopsys.com>

    [ Upstream commit 92a8dd26464e1f21f1d869ec53717bd2c1200d63 ]

    Added missing GUSBCFG programming in host mode, which fixes
    transaction errors issue on HiKey and Altera Cyclone V boards.

    These field even if was programmed in device mode (in function
    dwc2_hsotg_core_init_disconnected()) will be resetting to POR values
    after core soft reset applied.
    So, each time when switching to host mode required to set this field
    to correct value.

    Acked-by: John Youn <johnyoun@synopsys.com>
    Signed-off-by: Minas Harutyunyan <hminas@synopsys.com>
    Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com>
    Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/usb/dwc2/hcd.c | 14 +++++++++++++-
    1 file changed, 13 insertions(+), 1 deletion(-)

    --- a/drivers/usb/dwc2/hcd.c
    +++ b/drivers/usb/dwc2/hcd.c
    @@ -2340,10 +2340,22 @@ static int dwc2_core_init(struct dwc2_hs
    */
    static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
    {
    - u32 hcfg, hfir, otgctl;
    + u32 hcfg, hfir, otgctl, usbcfg;

    dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);

    + /* Set HS/FS Timeout Calibration to 7 (max available value).
    + * The number of PHY clocks that the application programs in
    + * this field is added to the high/full speed interpacket timeout
    + * duration in the core to account for any additional delays
    + * introduced by the PHY. This can be required, because the delay
    + * introduced by the PHY in generating the linestate condition
    + * can vary from one PHY to another.
    + */
    + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
    + usbcfg |= GUSBCFG_TOUTCAL(7);
    + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
    +
    /* Restart the Phy Clock */
    dwc2_writel(0, hsotg->regs + PCGCTL);


    \
     
     \ /
      Last update: 2018-05-24 12:03    [W:4.087 / U:1.104 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site