Messages in this thread Patch in this message | | | From | Stefan Agner <> | Subject | [RESEND PATCH 3/5] clk: tegra20: init NDFLASH clock to sensible rate | Date | Tue, 22 May 2018 14:07:07 +0200 |
| |
From: Lucas Stach <dev@lynxeye.de>
Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stefan Agner <stefan@agner.ch> --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 0ee56dd04cec..dff8c425cd28 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; -- 2.17.0
| |