Messages in this thread | | | Subject | Re: [PATCH v10 02/27] clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE | From | David Lechner <> | Date | Tue, 15 May 2018 10:42:54 -0500 |
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On 05/15/2018 08:31 AM, Sekhar Nori wrote: > On Wednesday 09 May 2018 10:55 PM, David Lechner wrote: >> +void of_da850_pll0_init(struct device_node *node) >> { >> - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, >> - &da850_pll0_obsclk_info, >> - da850_pll0_sysclk_info, 7, base, cfgchip); >> + void __iomem *base; >> + struct regmap *cfgchip; >> + >> + base = of_iomap(node, 0); >> + if (!base) { >> + pr_err("%s: ioremap failed\n", __func__); >> + return; >> + } >> + >> + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
In your previous review, you pointed out that the error did not need to be handled here because it is handled later in davinci_pll_clk_register().
We get a warning there because cfgchip is only needed for unlocking the PLL for CPU frequency scaling and is not critical for operation of the clocks.
> > It will be nice to handle the error case here. > >> + >> + of_davinci_pll_init(NULL, node, &da850_pll0_info, >> + &da850_pll0_obsclk_info, >> + da850_pll0_sysclk_info, 7, base, cfgchip); > > Apart from that, it looks good to me. > > Reviewed-by: Sekhar Nori <nsekhar@ti.com> > > Thanks, > Sekhar >
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