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    Subject[4.15 & 4.14 stable 05/12] x86/microcode/intel: Check microcode revision before updating sibling threads
    Date
    commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream

    After updating microcode on one of the threads of a core, the other
    thread sibling automatically gets the update since the microcode
    resources on a hyperthreaded core are shared between the two threads.

    Check the microcode revision on the CPU before performing a microcode
    update and thus save us the WRMSR 0x79 because it is a particularly
    expensive operation.

    [ Borislav: Massage changelog and coding style. ]

    Signed-off-by: Ashok Raj <ashok.raj@intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
    Tested-by: Ashok Raj <ashok.raj@intel.com>
    Cc: Tom Lendacky <thomas.lendacky@amd.com>
    Cc: Asit K Mallick <asit.k.mallick@intel.com>
    Cc: stable@vger.kernel.org
    Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
    Link: http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok.raj@intel.com
    Link: https://lkml.kernel.org/r/20180228102846.13447-3-bp@alien8.de
    ---
    arch/x86/kernel/cpu/microcode/intel.c | 27 ++++++++++++++++++++++++---
    1 file changed, 24 insertions(+), 3 deletions(-)

    diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
    index 923054a..87bd6dc 100644
    --- a/arch/x86/kernel/cpu/microcode/intel.c
    +++ b/arch/x86/kernel/cpu/microcode/intel.c
    @@ -589,6 +589,17 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
    if (!mc)
    return 0;

    + /*
    + * Save us the MSR write below - which is a particular expensive
    + * operation - when the other hyperthread has updated the microcode
    + * already.
    + */
    + rev = intel_get_microcode_revision();
    + if (rev >= mc->hdr.rev) {
    + uci->cpu_sig.rev = rev;
    + return UCODE_OK;
    + }
    +
    /* write microcode via MSR 0x79 */
    native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);

    @@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_intel(int cpu)
    {
    struct microcode_intel *mc;
    struct ucode_cpu_info *uci;
    - struct cpuinfo_x86 *c;
    + struct cpuinfo_x86 *c = &cpu_data(cpu);
    static int prev_rev;
    u32 rev;

    @@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_intel(int cpu)
    return UCODE_NFOUND;
    }

    + /*
    + * Save us the MSR write below - which is a particular expensive
    + * operation - when the other hyperthread has updated the microcode
    + * already.
    + */
    + rev = intel_get_microcode_revision();
    + if (rev >= mc->hdr.rev) {
    + uci->cpu_sig.rev = rev;
    + c->microcode = rev;
    + return UCODE_OK;
    + }
    +
    /* write microcode via MSR 0x79 */
    wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);

    @@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_intel(int cpu)
    prev_rev = rev;
    }

    - c = &cpu_data(cpu);
    -
    uci->cpu_sig.rev = rev;
    c->microcode = rev;

    --
    2.7.4
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