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    Subject[PATCH 4.14 137/183] MIPS: Generic: Support GIC in EIC mode
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Matt Redfearn <matt.redfearn@mips.com>


    [ Upstream commit 7bf8b16d1b60419c865e423b907a05f413745b3e ]

    The GIC supports running in External Interrupt Controller (EIC) mode,
    and will signal this via cpu_has_veic if enabled in hardware. Currently
    the generic kernel will panic if cpu_has_veic is set - but the GIC can
    legitimately set this flag if either configured to boot in EIC mode, or
    if the GIC driver enables this mode. Make the kernel not panic in this
    case, and instead just check if the GIC is present. If so, use it's CPU
    local interrupt routing functions. If an EIC is present, but it is not
    the GIC, then the kernel does not know how to get the VIRQ for the CPU
    local interrupts and should panic. Support for alternative EICs being
    present is needed here for the generic kernel to support them.

    Suggested-by: Paul Burton <paul.burton@mips.com>
    Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/18191/
    Signed-off-by: James Hogan <jhogan@kernel.org>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/mips/generic/irq.c | 18 +++++++++---------
    1 file changed, 9 insertions(+), 9 deletions(-)

    --- a/arch/mips/generic/irq.c
    +++ b/arch/mips/generic/irq.c
    @@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
    {
    int mips_cpu_fdc_irq;

    - if (cpu_has_veic)
    - panic("Unimplemented!");
    - else if (mips_gic_present())
    + if (mips_gic_present())
    mips_cpu_fdc_irq = gic_get_c0_fdc_int();
    + else if (cpu_has_veic)
    + panic("Unimplemented!");
    else if (cp0_fdc_irq >= 0)
    mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
    else
    @@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
    {
    int mips_cpu_perf_irq;

    - if (cpu_has_veic)
    - panic("Unimplemented!");
    - else if (mips_gic_present())
    + if (mips_gic_present())
    mips_cpu_perf_irq = gic_get_c0_perfcount_int();
    + else if (cpu_has_veic)
    + panic("Unimplemented!");
    else if (cp0_perfcount_irq >= 0)
    mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
    else
    @@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
    {
    int mips_cpu_timer_irq;

    - if (cpu_has_veic)
    - panic("Unimplemented!");
    - else if (mips_gic_present())
    + if (mips_gic_present())
    mips_cpu_timer_irq = gic_get_c0_compare_int();
    + else if (cpu_has_veic)
    + panic("Unimplemented!");
    else
    mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;


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