Messages in this thread Patch in this message | | | From | Masanari Iida <> | Subject | [PATCH] perf vendor events intel: Fix double words "are are" in cache.json | Date | Wed, 25 Apr 2018 00:02:49 +0900 |
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This patch fix double words "are are".
Signed-off-by: Masanari Iida <standby24x7@gmail.com> --- tools/perf/pmu-events/arch/x86/silvermont/cache.json | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json index 82be7d1b8b81..d961a8cb8215 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -641,7 +641,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Offcore": "1" }, { @@ -696,7 +696,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "BriefDescription": "Counts demand and DCU prefetch RFOs that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Offcore": "1" }, { @@ -751,7 +751,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "BriefDescription": "Counts demand and DCU prefetch data read that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Offcore": "1" }, { @@ -809,4 +809,4 @@ "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", "Offcore": "1" } -] \ No newline at end of file +] -- 2.17.0.140.g0b0cc9f86731
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