Messages in this thread | | | Subject | Re: [PATCH v4 1/3] perf/core: store context switch out type into Perf trace | From | Alexey Budankov <> | Date | Thu, 29 Mar 2018 21:02:21 +0300 |
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Hi,
On 29.03.2018 18:43, Mark Rutland wrote: > Hi, > > On Thu, Mar 29, 2018 at 06:02:48PM +0300, Alexey Budankov wrote: >> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h >> index 912b85b52344..cd6ad7e13824 100644 >> --- a/include/uapi/linux/perf_event.h >> +++ b/include/uapi/linux/perf_event.h >> @@ -655,6 +655,10 @@ struct perf_event_mmap_page { >> * perf_event_attr::precise_ip. >> */ >> #define PERF_RECORD_MISC_EXACT_IP (1 << 14) >> +/* >> + * Indicates that thread was preempted in TASK_RUNNING state >> + */ >> +#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) >> /* >> * Reserve the last bit to indicate some extended misc field >> */ > > Could you please add a description (in the header) describing why it's safe to > reuse this bit? i.e. describe which events these are valid for, so it's clear > they don't overlap.
It is currently employed only on x86 architecture when reporting precise events samples with exact bit set in pt_regs->flags. Apparently there is no conflict on this bit among different trace records so the message could be like this:
/* * These PERF_RECORD_MISC_* flags are safely reused for the following events: * * PERF_RECORD_MISC_PRECISE_IP - PERF_RECORD_SAMPLE of precise events * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events */
Thanks, Alexey
> > For bit 13 we have: > > /* > * Following PERF_RECORD_MISC_* are used on different > * events, so can reuse the same bit position: > * > * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events > * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event > * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events > */ > #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) > #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) > #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) > > Thanks, > Mark. >
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