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    Subject[PATCH 4.15 59/84] pinctrl: rockchip: enable clock when reading pin direction register
    Date
    4.15-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Brian Norris <briannorris@chromium.org>


    [ Upstream commit 5c9d8c4f6b8168738a26bcf288516cc3a0886810 ]

    We generally leave the GPIO clock disabled, unless an interrupt is
    requested or we're accessing IO registers. We forgot to do this for the
    ->get_direction() callback, which means we can sometimes [1] get
    incorrect results [2] from, e.g., /sys/kernel/debug/gpio.

    Enable the clock, so we get the right results!

    [1] Sometimes, because many systems have 1 or mor interrupt requested on
    each GPIO bank, so they always leave their clock on.

    [2] Incorrect, meaning the register returns 0, and so we interpret that
    as "input".

    Signed-off-by: Brian Norris <briannorris@chromium.org>
    Reviewed-by: Heiko Stuebner <heiko@sntech.de>
    Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pinctrl/pinctrl-rockchip.c | 8 ++++++++
    1 file changed, 8 insertions(+)

    --- a/drivers/pinctrl/pinctrl-rockchip.c
    +++ b/drivers/pinctrl/pinctrl-rockchip.c
    @@ -2014,8 +2014,16 @@ static int rockchip_gpio_get_direction(s
    {
    struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
    u32 data;
    + int ret;

    + ret = clk_enable(bank->clk);
    + if (ret < 0) {
    + dev_err(bank->drvdata->dev,
    + "failed to enable clock for bank %s\n", bank->name);
    + return ret;
    + }
    data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
    + clk_disable(bank->clk);

    return !(data & BIT(offset));
    }

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