Messages in this thread | | | Date | Thu, 22 Mar 2018 00:11:56 +0000 | From | James Hogan <> | Subject | Re: [PATCH v3] MIPS: ralink: fix booting on mt7621 |
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On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining that mips_cm_probe() > "wipes out the bootloader config" and means that configuration > registers are no longer available. It has some code to re-enable > this config. > > Before this re-enable code is run, the sysc register cannot be > read, so when SYSC_REG_CHIP_NAME0 is read, a garbage value > is returned and panic() is called. > > If we move the config-repair code to the top of prom_soc_init(), > the registers can be read and boot can proceed. > > Very occasionally, the first register read after the reconfiguration > returns garbage. So I added a call to __sync(). > > Fixes: 3af5a67c86a3 ("MIPS: Fix early CM probing") > Signed-off-by: NeilBrown <neil@brown.name>
Looks good. I've cosmetically tweaked commit message (mainly reflow), added stable tag for 4.5+, and applied for 4.16.
Thanks James [unhandled content-type:application/pgp-signature] | |