Messages in this thread | | | Date | Wed, 21 Mar 2018 11:00:38 +0800 | From | Wu Hao <> | Subject | Re: [PATCH v4 23/24] fpga: dfl: afu: add user afu sub feature support |
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On Tue, Mar 20, 2018 at 01:17:14PM -0500, Alan Tull wrote: > On Tue, Mar 20, 2018 at 2:10 AM, Wu Hao <hao.wu@intel.com> wrote: > > On Mon, Mar 19, 2018 at 03:10:28PM -0500, Alan Tull wrote: > >> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao.wu@intel.com> wrote: > >> > >> Hi Hao, > >> > >> > From: Xiao Guangrong <guangrong.xiao@linux.intel.com> > >> > > >> > User Accelerated Function Unit sub feature exposes the MMIO region of > >> > >> Is it 'user accelerated'? I think it is the Accelerator interface. > > > > Hi Alan, > > > > This is only used to emphasize this is the interface to accelerator > > exposed to user. But looks like this causes some confusions for user > > actually from the description. I agree with you, that I will remove > > this UAFU from this patchset. > > > >> > >> > the AFU. After valid green bitstream (GBS) is programmed and port is > >> > >> Would it make sense to just use "partial bitstream" or "PR bitstream" > >> and "static bitstream" for this patchset? I don't think that adding > >> this terminology makes things clearer. In any case when someone else > >> uses this patchset, they may not be using this type of branding in > >> their terminology. > > > > Sure, will update the commit message and also sysfs doc below. > > Yes and dfl.txt and the rest of the patchset as well, please.
Sure, I understand that it may have different PR hardwares under this framework, each PR hardware may have a different terminology for its own bitstream. We should use common terminology in the common doc and code to avoid confusion. Thanks for the reminder. I will fix this.
Thanks Hao
> > Alan
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