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    SubjectRe: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available
    On Wed, Mar 14, 2018 at 11:15:47AM +0000, Marc Zyngier wrote:
    > Hi Matt,
    >
    > On 05/01/18 10:31, Matt Redfearn wrote:
    > >
    > > This series enables the MIPS GIC driver to make use of the EIC mode
    > > supported in some MIPS cores. In this mode, the cores 6 interrupt lines
    > > are switched to represent a vector number, 0..63. Currently all GIC
    > > interrupts are routed to a single CPU interrupt pin, but this is
    > > inefficient since we end up checking both local and shared interrupt
    > > flag registers for both local and shared interrupts. This introduces
    > > additional latency into the interrupt paths. With EIC mode this can be
    > > improved by using separate vectors for local and shared interrupts.
    > >
    > > This series is based on 4.15-rc6 and has been tested on Boston, Malta &
    > > SEAD3 MIPS platforms implementing a GIC with and without EIC mode
    > > supported in hardware.
    >
    > What the status of this series?

    FYI I've been meaning to test it with KVM, since host EIC I think will
    affect KVM & guest stuff.

    Cheers
    James
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