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SubjectRe: [PATCH v7 01/42] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
On Mon, Feb 19, 2018 at 02:21:22PM -0600, David Lechner wrote:
> This adds a new binding for the PLL IP blocks in the mach-davinci
> family of processors. Currently, only da850 has device tree support
> but these bindings can also work for other SoCs in this family just
> by adding new compatible strings.
>
> Note: Although these PLL controllers are very similar to the TI Keystone
> SoCs, we are not re-using those bindings. The Keystone bindings use a
> legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
> have a slightly different PLL register layout and a number of quirks
> that can't be handled by the existing bindings, so the keystone bindings
> could not be used as-is anyway.
>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
>
> v7 changes:
> - None (there was some debate about having child nodes, but the consensus was
> that this is "good enough" as it is)
>
> v6 changes:
> - Added clock-names property
> - Added ti,clkmode-square-wave property
> - Added pllout child node
> - Added obsclk child node
> - Expanded examples
>
>
> .../devicetree/bindings/clock/ti/davinci/pll.txt | 96 ++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt

Reviewed-by: Rob Herring <robh@kernel.org>

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