Messages in this thread | | | Date | Mon, 5 Feb 2018 00:08:31 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v2 1/5] clk: mediatek: update missing clock data for MT7622 audsys |
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On Wed, Jan 31, 2018 at 03:42:41PM +0800, Ryder Lee wrote: > Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. > > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > --- > drivers/clk/mediatek/clk-mt7622-aud.c | 1 + > include/dt-bindings/clock/mt7622-clk.h | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Rob Herring <robh@kernel.org>
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