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    Subject[PATCH 4.4 09/67] bpf: fix 32-bit divide by zero
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Alexei Starovoitov <ast@kernel.org>

    [ upstream commit 68fda450a7df51cff9e5a4d4a4d9d0d5f2589153 ]

    due to some JITs doing if (src_reg == 0) check in 64-bit mode
    for div/mod operations mask upper 32-bits of src register
    before doing the check

    Fixes: 622582786c9e ("net: filter: x86: internal BPF JIT")
    Fixes: 7a12b5031c6b ("sparc64: Add eBPF JIT.")
    Reported-by: syzbot+48340bb518e88849e2e3@syzkaller.appspotmail.com
    Signed-off-by: Alexei Starovoitov <ast@kernel.org>
    Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    kernel/bpf/verifier.c | 18 ++++++++++++++++++
    net/core/filter.c | 4 ++++
    2 files changed, 22 insertions(+)

    --- a/kernel/bpf/verifier.c
    +++ b/kernel/bpf/verifier.c
    @@ -2248,6 +2248,24 @@ static int fixup_bpf_calls(struct verifi
    int i, cnt, delta = 0;

    for (i = 0; i < insn_cnt; i++, insn++) {
    + if (insn->code == (BPF_ALU | BPF_MOD | BPF_X) ||
    + insn->code == (BPF_ALU | BPF_DIV | BPF_X)) {
    + /* due to JIT bugs clear upper 32-bits of src register
    + * before div/mod operation
    + */
    + insn_buf[0] = BPF_MOV32_REG(insn->src_reg, insn->src_reg);
    + insn_buf[1] = *insn;
    + cnt = 2;
    + new_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);
    + if (!new_prog)
    + return -ENOMEM;
    +
    + delta += cnt - 1;
    + env->prog = prog = new_prog;
    + insn = new_prog->insnsi + i + delta;
    + continue;
    + }
    +
    if (insn->code != (BPF_JMP | BPF_CALL))
    continue;

    --- a/net/core/filter.c
    +++ b/net/core/filter.c
    @@ -430,6 +430,10 @@ do_pass:
    convert_bpf_extensions(fp, &insn))
    break;

    + if (fp->code == (BPF_ALU | BPF_DIV | BPF_X) ||
    + fp->code == (BPF_ALU | BPF_MOD | BPF_X))
    + *insn++ = BPF_MOV32_REG(BPF_REG_X, BPF_REG_X);
    +
    *insn = BPF_RAW_INSN(fp->code, BPF_REG_A, BPF_REG_X, 0, fp->k);
    break;


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