lkml.org 
[lkml]   [2018]   [Dec]   [13]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Subject[PATCH v2 0/4] Timer code cleanup.
    Date

    This patch series provides an assorted timer cleanups in RISC-V.

    Changes from v1->v2:

    1. Updated commit text in 1/4.
    2. Added a timebase check for each cpu.
    3. Added a warning for invalid hartid 4/4.

    Atish Patra (3):
    RISC-V: Support per-hart timebase-frequency
    RISC-V: Remove per cpu clocksource
    RISC-V: Fix non-smp kernel boot on SMP systems

    Palmer Dabbelt (1):
    dt-bindings: Correct RISC-V's timebase-frequency

    Documentation/devicetree/bindings/riscv/cpus.txt | 4 +-
    arch/riscv/kernel/time.c | 9 +----
    drivers/clocksource/riscv_timer.c | 51 +++++++++++++++++++++---
    3 files changed, 49 insertions(+), 15 deletions(-)

    --
    2.7.4

    \
     
     \ /
      Last update: 2018-12-14 00:15    [W:3.159 / U:0.136 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site