Messages in this thread | | | From | Andy Lutomirski <> | Date | Wed, 12 Dec 2018 10:07:03 -0800 | Subject | Re: [RFC PATCH 4/4] x86/TSC: Use RDTSCP |
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On Wed, Dec 12, 2018 at 2:08 AM Borislav Petkov <bp@alien8.de> wrote: > > On Tue, Dec 11, 2018 at 06:24:44PM -0800, Andy Lutomirski wrote: > > This makes me nervous, since no one knows what “serializing” means. > > Why no one? If you wanna say that X86_FEATURE_LFENCE_SERIALIZING is not > really telling, so is X86_FEATURE_LFENCE_RDTSC, TBH. :)
You're proving my point, I think. CPUID, IRET, MOV to CR, etc are "serializing". LFENCE, on many CPUd and depending on MSRs, is a different kind of serializing. MFENCE is something else. All LOCK instructions are some kind of barrier, but I don't think anyone calls them "serializing".
The uaccess users of barrier_nospec() are presumably looking for a speculation barrier in the sense of "CPU, please don't execute the code after this until you're sure that this code should be executed for real and until all inputs are known, not guessed."
The property I want for RDTSC ordering is much weaker: I want it to be ordered like a load. Imagine that, instead of an on-chip TSC, the TSC is literally a location in main memory that gets incremented by an extra dedicated CPU every nanosecond or so. I want users of RDTSC to work as if they were reading such a location in memory using an ordinary load. I believe this gives the real desired property that it should be impossible to observe the TSC going backwards. This is a much weaker form of serialization.
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