Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v9 3/5] clk: imx: add SCCG PLL type | Date | Wed, 07 Nov 2018 16:18:35 -0800 |
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Quoting Abel Vesa (2018-11-07 12:26:25) > On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote: > > > > > > What's the plan to clean it up? > > So I'm doing this in our internal tree first to make sure I don't break the > other (newer) socs. > > I already have a prototype in testing but it's a long way to upstream it. > > Basically, I'm replacing all of this with a single, more like a composite, > more complex, clock type that does all the magic inside. > > One of the problems is the fact that the bypasses can have the same sources > and in my case, I'm implementing that as a list of parents name, but the > parent names list doesn't work with duplicates, so I have to find some other > way to do it. > > Once I have something clean and tested enough I'll send it upstream.
Ok. Thanks for the info.
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