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    Subject[tip:x86/pti] x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support
    Commit-ID:  20ffa1caecca4db8f79fe665acdeaa5af815a24d
    Gitweb: https://git.kernel.org/tip/20ffa1caecca4db8f79fe665acdeaa5af815a24d
    Author: David Woodhouse <dwmw@amazon.co.uk>
    AuthorDate: Thu, 25 Jan 2018 16:14:15 +0000
    Committer: Thomas Gleixner <tglx@linutronix.de>
    CommitDate: Fri, 26 Jan 2018 15:53:18 +0100

    x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support

    Expose indirect_branch_prediction_barrier() for use in subsequent patches.

    [ tglx: Add IBPB status to spectre_v2 sysfs file ]

    Co-developed-by: KarimAllah Ahmed <karahmed@amazon.de>
    Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de>
    Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
    Cc: gnomes@lxorguk.ukuu.org.uk
    Cc: ak@linux.intel.com
    Cc: ashok.raj@intel.com
    Cc: dave.hansen@intel.com
    Cc: arjan@linux.intel.com
    Cc: torvalds@linux-foundation.org
    Cc: peterz@infradead.org
    Cc: bp@alien8.de
    Cc: pbonzini@redhat.com
    Cc: tim.c.chen@linux.intel.com
    Cc: gregkh@linux-foundation.org
    Link: https://lkml.kernel.org/r/1516896855-7642-8-git-send-email-dwmw@amazon.co.uk

    ---
    arch/x86/include/asm/cpufeatures.h | 2 ++
    arch/x86/include/asm/nospec-branch.h | 13 +++++++++++++
    arch/x86/kernel/cpu/bugs.c | 10 +++++++++-
    3 files changed, 24 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index ae3212f..07934b2 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -210,6 +210,8 @@
    #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
    #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */

    +#define X86_FEATURE_IBPB ( 7*32+21) /* Indirect Branch Prediction Barrier enabled*/
    +
    /* Virtualization flags: Linux defined, word 8 */
    #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
    #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
    diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
    index 4ad4108..34e384c 100644
    --- a/arch/x86/include/asm/nospec-branch.h
    +++ b/arch/x86/include/asm/nospec-branch.h
    @@ -218,5 +218,18 @@ static inline void vmexit_fill_RSB(void)
    #endif
    }

    +static inline void indirect_branch_prediction_barrier(void)
    +{
    + asm volatile(ALTERNATIVE("",
    + "movl %[msr], %%ecx\n\t"
    + "movl %[val], %%eax\n\t"
    + "movl $0, %%edx\n\t"
    + "wrmsr",
    + X86_FEATURE_IBPB)
    + : : [msr] "i" (MSR_IA32_PRED_CMD),
    + [val] "i" (PRED_CMD_IBPB)
    + : "eax", "ecx", "edx", "memory");
    +}
    +
    #endif /* __ASSEMBLY__ */
    #endif /* __NOSPEC_BRANCH_H__ */
    diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
    index 4a39d7b..bac7a35 100644
    --- a/arch/x86/kernel/cpu/bugs.c
    +++ b/arch/x86/kernel/cpu/bugs.c
    @@ -263,6 +263,13 @@ retpoline_auto:
    setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
    pr_info("Filling RSB on context switch\n");
    }
    +
    + /* Initialize Indirect Branch Prediction Barrier if supported */
    + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) ||
    + boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) {
    + setup_force_cpu_cap(X86_FEATURE_IBPB);
    + pr_info("Enabling Indirect Branch Prediction Barrier\n");
    + }
    }

    #undef pr_fmt
    @@ -292,7 +299,8 @@ ssize_t cpu_show_spectre_v2(struct device *dev,
    if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
    return sprintf(buf, "Not affected\n");

    - return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled],
    + return sprintf(buf, "%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
    + boot_cpu_has(X86_FEATURE_IBPB) ? ", IPBP" : "",
    spectre_v2_bad_module ? " - vulnerable module loaded" : "");
    }
    #endif
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