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    SubjectRe: [PATCH v2 4/5] x86/msr: Add definitions for new speculation control MSRs
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    On 01/23/2018 08:52 AM, David Woodhouse wrote:
    > +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
    > +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
    > +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */

    Do we want to spell out the silly Intel acronym? I don't know how we
    fit it on the right side, but I do think we need to do it _somewhere_.
    We need the code to stand on its own to some degree and not subject the
    masses to reading the spec to understand the code.

    /* Not to susceptible Rogue Data Cache Load aka Meltdown: */
    #define ARCH_CAP_RDCL_NO (1 << 0)

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