lkml.org 
[lkml]   [2018]   [Jan]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 0/4] Add support for Intel IOMMU 5-level paging
On Wed, Dec 20, 2017 at 11:59:23AM -0800, Sohil Mehta wrote:
> Sohil Mehta (4):
> iommu/vt-d: Enable upto 57 bits of domain address width
> iommu/vt-d: Add a check for 1GB page support
> iommu/vt-d: Add a check for 5-level paging support
> iommu/vt-d: Enable 5-level paging mode in the PASID entry
>
> drivers/iommu/intel-iommu.c | 2 +-
> drivers/iommu/intel-svm.c | 23 +++++++++++++++++++++--
> include/linux/intel-iommu.h | 2 ++
> 3 files changed, 24 insertions(+), 3 deletions(-)

Applied, thanks.

\
 
 \ /
  Last update: 2018-01-18 00:20    [W:0.645 / U:0.164 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site