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    Subject[PATCH 4.14 097/118] x86/cpu/AMD: Make LFENCE a serializing instruction
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Tom Lendacky <thomas.lendacky@amd.com>

    commit e4d0e84e490790798691aaa0f2e598637f1867ec upstream.

    To aid in speculation control, make LFENCE a serializing instruction
    since it has less overhead than MFENCE. This is done by setting bit 1
    of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not
    have this MSR. For these families, the LFENCE instruction is already
    serializing.

    Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Tim Chen <tim.c.chen@linux.intel.com>
    Cc: Dave Hansen <dave.hansen@intel.com>
    Cc: Borislav Petkov <bp@alien8.de>
    Cc: Dan Williams <dan.j.williams@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
    Cc: David Woodhouse <dwmw@amazon.co.uk>
    Cc: Paul Turner <pjt@google.com>
    Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/include/asm/msr-index.h | 2 ++
    arch/x86/kernel/cpu/amd.c | 10 ++++++++++
    2 files changed, 12 insertions(+)

    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -352,6 +352,8 @@
    #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
    #define FAM10H_MMIO_CONF_BASE_SHIFT 20
    #define MSR_FAM10H_NODE_ID 0xc001100c
    +#define MSR_F10H_DECFG 0xc0011029
    +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1

    /* K8 MSRs */
    #define MSR_K8_TOP_MEM1 0xc001001a
    --- a/arch/x86/kernel/cpu/amd.c
    +++ b/arch/x86/kernel/cpu/amd.c
    @@ -829,6 +829,16 @@ static void init_amd(struct cpuinfo_x86
    set_cpu_cap(c, X86_FEATURE_K8);

    if (cpu_has(c, X86_FEATURE_XMM2)) {
    + /*
    + * A serializing LFENCE has less overhead than MFENCE, so
    + * use it for execution serialization. On families which
    + * don't have that MSR, LFENCE is already serializing.
    + * msr_set_bit() uses the safe accessors, too, even if the MSR
    + * is not present.
    + */
    + msr_set_bit(MSR_F10H_DECFG,
    + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
    +
    /* MFENCE stops RDTSC speculation */
    set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
    }

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