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    SubjectRe: [PATCH 4/5] x86/svm: Direct access to MSR_IA32_SPEC_CTRL
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    On 1/11/2018 7:32 PM, Ashok Raj wrote:
    > From: Paolo Bonzini <pbonzini@redhat.com>
    >
    > Direct access to MSR_IA32_SPEC_CTRL is important
    > for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore guest
    > IBRS on VM entry and set restore host values on VM exit.
    > it yet).
    >
    > TBD: need to check msr's can be passed through even if feature is not
    > emuerated by the CPU.
    >
    > [Ashok: Modified to reuse V3 spec-ctrl patches from Tim]
    >
    > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
    > Signed-off-by: Ashok Raj <ashok.raj@intel.com>
    > ---
    > arch/x86/kvm/svm.c | 35 +++++++++++++++++++++++++++++++++++
    > 1 file changed, 35 insertions(+)
    >
    > diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
    > index 0e68f0b..7c14471a 100644
    > --- a/arch/x86/kvm/svm.c
    > +++ b/arch/x86/kvm/svm.c
    > @@ -183,6 +183,8 @@ struct vcpu_svm {
    > u64 gs_base;
    > } host;
    >
    > + u64 spec_ctrl;
    > +
    > u32 *msrpm;
    >
    > ulong nmi_iret_rip;
    > @@ -248,6 +250,7 @@ static const struct svm_direct_access_msrs {
    > { .index = MSR_CSTAR, .always = true },
    > { .index = MSR_SYSCALL_MASK, .always = true },
    > #endif
    > + { .index = MSR_IA32_SPEC_CTRL, .always = true },
    > { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
    > { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
    > { .index = MSR_IA32_LASTINTFROMIP, .always = false },
    > @@ -917,6 +920,9 @@ static void svm_vcpu_init_msrpm(u32 *msrpm)
    >
    > set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
    > }
    > +
    > + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
    > + set_msr_interception(msrpm, MSR_IA32_SPEC_CTRL, 1, 1);

    This isn't needed. The entry in the direct_access_msrs will do this in
    the loop above.

    Thanks,
    Tom

    > }
    >
    > static void add_msr_offset(u32 offset)
    > @@ -3576,6 +3582,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    > case MSR_VM_CR:
    > msr_info->data = svm->nested.vm_cr_msr;
    > break;
    > + case MSR_IA32_SPEC_CTRL:
    > + msr_info->data = svm->spec_ctrl;
    > + break;
    > case MSR_IA32_UCODE_REV:
    > msr_info->data = 0x01000065;
    > break;
    > @@ -3724,6 +3733,9 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
    > case MSR_VM_IGNNE:
    > vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
    > break;
    > + case MSR_IA32_SPEC_CTRL:
    > + svm->spec_ctrl = data;
    > + break;
    > case MSR_IA32_APICBASE:
    > if (kvm_vcpu_apicv_active(vcpu))
    > avic_update_vapic_bar(to_svm(vcpu), data);
    > @@ -4871,6 +4883,19 @@ static void svm_cancel_injection(struct kvm_vcpu *vcpu)
    > svm_complete_interrupts(svm);
    > }
    >
    > +
    > +/*
    > + * Save guest value of spec_ctrl and also restore host value
    > + */
    > +static void save_guest_spec_ctrl(struct vcpu_svm *svm)
    > +{
    > + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
    > + svm->spec_ctrl = spec_ctrl_get();
    > + spec_ctrl_restriction_on();
    > + } else
    > + rmb();
    > +}
    > +
    > static void svm_vcpu_run(struct kvm_vcpu *vcpu)
    > {
    > struct vcpu_svm *svm = to_svm(vcpu);
    > @@ -4910,6 +4935,14 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
    >
    > clgi();
    >
    > + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
    > + /*
    > + * FIXME: lockdep_assert_irqs_disabled();
    > + */
    > + WARN_ON_ONCE(!irqs_disabled());
    > + spec_ctrl_set(svm->spec_ctrl);
    > + }
    > +
    > local_irq_enable();
    >
    > asm volatile (
    > @@ -4985,6 +5018,8 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
    > #endif
    > );
    >
    > + save_guest_spec_ctrl(svm);
    > +
    > #ifdef CONFIG_X86_64
    > wrmsrl(MSR_GS_BASE, svm->host.gs_base);
    > #else
    >

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