Messages in this thread | | | Date | Wed, 10 Jan 2018 14:46:22 +0100 (CET) | From | Thomas Gleixner <> | Subject | Re: [patch RFC 5/5] x86/speculation: Add basic speculation control code |
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On Wed, 10 Jan 2018, David Woodhouse wrote: > Andrea, what you're saying is directly contradicting what I've heard > from Intel. > > The documentation already distinguishes between IBRS on current > hardware, and IBRS_ATT on future hardware. If it was the case that IBRS > on current hardware is a set-and-forget option and completely disables > branch prediction, then they would say that. Rather than explicitly > saying the *opposite*, specifically for the case of current hardware, > as they do. > > Rather than continuing to debate it, perhaps it's best just to wake for > the US to wake up, and Intel to give a definitive answer.
So here is the simple list of questions all to be answered with YES or NO. I don't want to see any of the 'but, though ...'. We all know by now that it's CPU dependent and slow and whatever and that IBRS_ATT will be in future CPUs. So get your act together and tell a clear YES or NO.
1) Does IBRS=1 when set once act as a set-and-forget option ?
1a) If the answer to #1 is yes, is it more secure than toggling it?
1b) If the answer to #1 is yes, is retpoline required ?
1c) If the answer to #1 is yes, is RSB stuffing required ?
2) Does toggle mode of IBRS require retpoline ?
3) Does toggle mode of IBRS require RSB stuffing ?
4) Exist CPUs which require IBRS to be selected automatically ?
4b) If yes, provide the list as a separate answer please
Thanks,
tglx
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