Messages in this thread Patch in this message | | | From | kan.liang@intel ... | Subject | [PATCH 2/3] perf/x86/msr: add missing CPU IDs | Date | Fri, 8 Sep 2017 17:34:48 -0400 |
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From: Kan Liang <Kan.liang@intel.com>
Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.
Signed-off-by: Kan Liang <Kan.liang@intel.com> --- arch/x86/events/msr.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4bb3ec6..0672367 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -63,6 +63,14 @@ static bool test_intel(int idx) case INTEL_FAM6_ATOM_SILVERMONT1: case INTEL_FAM6_ATOM_SILVERMONT2: case INTEL_FAM6_ATOM_AIRMONT: + + case INTEL_FAM6_ATOM_GOLDMONT: + case INTEL_FAM6_ATOM_DENVERTON: + + case INTEL_FAM6_ATOM_GEMINI_LAKE: + + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (idx == PERF_MSR_SMI) return true; break; -- 2.9.4
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