Messages in this thread | | | Subject | Re: [PATCH] sound: soc: fsl: Do not set DAI sysclk when it is equal to system freq | From | Łukasz Majewski <> | Date | Tue, 5 Sep 2017 10:19:05 +0200 |
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On 09/05/2017 09:52 AM, Nicolin Chen wrote: > On Tue, Sep 05, 2017 at 09:37:43AM +0200, Łukasz Majewski wrote: > >>>> The last call is changing the bit clock (BCLK) frequency to SSI's IP >>>> block clock (ipg = 66 MHz) [1]. >>> >>> I think a bigger question here is why the routine sets BCLK to 66MHz. >> >> Yes, exactly. >> >> In my case the bclk is set to ipg clock, which is the SSI IP block clock >> (ipg). > > Can you elaborate why you set ipg clock as bclk? I don't remember SSI could > derive bitclock from ipg clock.
Just to be clear:
What clock shall be set with:
struct snd_soc_dai_ops {
int (*set_sysclk)(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir); }
callback?
The SSI IP block or BCLK ?
> >>>> This is wrong, since IMX SSI block requires the I2S BCLK to be less >>>> than 1/5 of [1]. >>>> >>>> As a result the driver initialization passes without any errors, but the >>>> speaker-test test case breaks. >>>> >>>> This commit checks if the fsl_ssi_set_dai_sysclk() frequency passed is >>>> not equal to [1]. >>> >>> I don't feel it's quite comprehensive...what if it's being set to 67MHz. >> >> I think that this clock is not changing for the SoC. It should be 66 MHz >> fixed. > > What I mean is that we cannot just look at this SoC. Today is 66MHz for this > SoC. Tomorrow could be 133MHz for another one. We should put a check that none > of these shall pass -- the 1/5 limit. >
Ok. Good point.
-- Best regards,
Lukasz Majewski
--
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