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Subject[PATCH 4.9 01/18] irqchip: mips-gic: SYNC after enabling GIC region
4.9-stable review patch.  If anyone has any objections, please let me know.


From: James Hogan <>

commit 2c0e8382386f618c85d20cb05e7cf7df8cdd382c upstream.

A SYNC is required between enabling the GIC region and actually trying
to use it, even if the first access is a read, otherwise its possible
depending on the timing (and in my case depending on the precise
alignment of certain kernel code) to hit CM bus errors on that first

Add the SYNC straight after setting the GIC base.

Changes later in this series increase our likelihood of hitting this
by reducing the amount of code that runs between enabling the GIC &
accessing it.]

Fixes: a7057270c280 ("irqchip: mips-gic: Add device-tree support")
Signed-off-by: James Hogan <>
Signed-off-by: Paul Burton <>
Acked-by: Marc Zyngier <>
Cc: Thomas Gleixner <>
Cc: Jason Cooper <>
Cc: James Hogan <>
Signed-off-by: Ralf Baechle <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/irqchip/irq-mips-gic.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -1115,8 +1115,11 @@ static int __init gic_of_init(struct dev
gic_len = resource_size(&res);

- if (mips_cm_present())
+ if (mips_cm_present()) {
write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
+ /* Ensure GIC region is enabled before trying to access it */
+ __sync();
+ }
gic_present = true;

__gic_init(gic_base, gic_len, cpu_vec, 0, node);

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